1. Field of the Invention
The present invention relates to a delay analyzer, a delay analyzing method, and computer product for estimating circuit delay.
2. Description of the Related Art
In recent years, the effect of statistical factors, such as process dispersion, power voltage drop, and crosstalk, on a semiconductor integrated circuit have increased as the size of the semiconductor integrated circuit has decreased, leading to an increase in circuit delay fluctuations. Conventional static delay analysis (static timing analysis (STA)) makes allowances for these circuit delay fluctuations as delay margins, but increasing delay margins make timing design difficult.
Under the circumstances, demand for statistical delay analysis (statistical static timing analysis (SSTA)) has been growing. The statistical delay analysis enables a reduction in unnecessary delay margins by precisely taking statistical factors into consideration. Statistical factors processed through SSTA include dispersion components independent between circuit elements and wires of a semiconductor integrated circuit, and dispersion components correlated between the circuit elements and wires.
Determining an exact delay distribution of the entire circuit through SSTA requires consideration of these dispersion components. For example, Monte Carlo simulation is one method for calculating an exact delay distribution of the entire circuit through consideration of dispersion components.
According to another proposed method, the components of relative dispersion of delay times resulting from opposite paths in an analysis subject circuit are divided into systematic components and random components, and a delay distribution of the entire circuit is calculated approximately using the systematic components and random components (e.g., see Japanese Patent Application Laid-Open Publication No. 2005-100310).
The Monte Carlo simulation, which is a conventional technique, however, requires an enormous amount of calculations to determine a delay distribution derived through precise consideration of dispersion factors. This method, therefore, requires greater work time for delay analysis, leading to a longer design period.
The conventional technique disclosed in Japanese Patent Application Laid-Open Publication No. 2005-100310 estimates statistical factors at worst values, thus giving a calculated delay distribution that is substantially pessimistic and inaccurate. As a result, review work in the course of circuit design becomes necessary, which increases burden on a designer and extends a design period.